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si823x data sheet 0.5 and 4.0 amp isodrivers (2.5 and 5 kv rms ) the si823x isolated driver family combines two independent, isolated drivers into a sin- gle package. the si8230/1/3/4 are high-side/low-side drivers, while the si8232/5/7/8 are dual drivers. versions with peak output currents of 0.5 a (si8230/1/2/7) and 4.0 a (si8233/4/5/8) are available. all drivers operate with a maximum supply voltage of 24 v. the si823x drivers utilize silicon labs' proprietary silicon isolation technology, which provides up to 5 kv rms withstand voltage per ul1577 and fast 45 ns propagation times. driver outputs can be grounded to the same or separate grounds or connected to a pos- itive or negative voltage. the ttl level compatible inputs with >400 mv hysteresis are available in individual control input (si8230/2/3/5/7/8) or pwm input (si8231/4) configu- rations. high integration, low propagation delay, small installed size, flexibility, and cost- effectiveness make the si823x family ideal for a wide range of isolated mosfet/igbt gate drive applications. automotive grade is available for certain part numbers. these products are built using automotive-specific flows at all steps in the manufacturing process to ensure the robust- ness and low defectivity required for automotive applications. key features ? two completely isolated drivers in one package ? up to 5 kv rms input-to-output isolation ? up to 1500 v dc peak driver-to-driver differential voltage ? hs/ls and dual driver versions ? up to 8 mhz switching frequency ? 0.5 a peak output (si8230/1/2/7) ? 4.0 a peak output (si8233/4/5/8) ? high electromagnetic immunity ? rohs-compliant packages: ? soic-14/16 wide body ? soic-16 narrow body ? lga-14 ? qfn-14 (pin to pin compatible with lga-14 packages) ? aec-q100 qualification ? automotive-grade opns available ? aiag compliant ppap documentation support ? imds and camds listing support industrial applications ? power delivery systems ? motor control systems ? isolated dc-dc power supplies ? lighting control systems ? plasma displays ? solar and industrial inverters safety regulatory approvals ? ul 1577 recognized ? up to 5000 v rms for 1 minute ? csa component notice 5a approval ? iec 60950-1, 62368-1, 60601-1 (re- inforced insulation) ? vde certification conformity ? vde 0884-10 ? en60950-1 (reinforced insulation) ? cqc certification approval ? gb4943.1 automotive applications ? on-board chargers ? battery management systems ? charging stations ? traction inverters ? hybrid electric vehicles ? battery electric vehicles silabs.com | building a more connected world. rev. 2.1.1
1. ordering guide table 1.1. si823x ordering guide 1, 2, 3 ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temp range package type legacy ordering part number (opn) 2.5 kv only wide body (wb) package options si8230bb-d-is via, vib high side/ low side 0.5 a 8 v 2.5 kvrms C40 to +125 c soic-16 wide body si8230-a-is si8231bb-d-is pwm high side/ low side si8231-a-is si8232bb-d-is via,vib dual driver si8232-a-is si8234cb-d-is pwm high side/ low side 4.0 a 10 v n/a si8233bb-d-is via,vib high side/ low side 8 v si8233-b-is si8234bb-d-is pwm high side/ low side si8234-b-is si8235bb-d-is via,vib dual driver si8235-b-is si8230ab-d-is via, vib high side/ low side 0.5 a 5 v 2.5 kvrms C40 to +125 c soic-16 wide body n/a si8231ab-d-is pwm n/a si8232ab-d-is via,vib dual driver n/a si8233ab-d-is via,vib high side/ low side 4.0 a 5 v n/a si8234ab-d-is pwm n/a si8235ab-d-is via,vib dual driver n/a narrow body (nb) package options si8230bb-d-is1 via,vib high side/ low side 0.5 a 8 v 2.5 kvrms C40 to +125 c soic-16 narrow body n/a si8231bb-d-is1 pwm high side/ low side si8232bb-d-is1 via,vib dual driver si8233bb-d-is1 via,vib high side/ low side 4.0 a 8 v si8234bb-d-is1 pwm high side/ low side si8235bb-d-is1 via,vib dual driver si8235ba-d-is1 via,vib dual driver 1.0 kvrms si823x data sheet ordering guide silabs.com | building a more connected world. rev. 2.1.1 | 2
ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temp range package type legacy ordering part number (opn) 2.5 kv only si8230ab-d-is1 via,vib high side/ low side 0.5 a 5 v 2.5 kvrms C40 to +125 c soic-16 narrow body n/a si8231ab-d-is1 pwm n/a si8232ab-d-is1 via,vib dual driver n/a si8233ab-d-is1 via,vib high side/ low side 4.0 a 5 v n/a si8234ab-d-is1 pwm n/a si8235ab-d-is1 via,vib dual driver n/a lga package options si8233cb-d-im via,vib high side/ low side 4.0 a 10 v 2.5 kvrms C40 to +125 c lga-14 5x5 mm n/a si8233bb-d-im 8 v si8233-b-im si8233ab-d-im 5 v n/a si8234bb-d-im pwm 8 v si8234-b-im si8234ab-d-im 5 v n/a si8235bb-d-im via,vib dual driver 8 v si8235-b-im si8235ab-d-im 5 v n/a qfn package options si8233ab-d-im1 via,vib high side/ low side 4.0 a 5 v 2.5 kvrms C40 to +125 c qfn-14 n/a si8233bb-d-im1 8 v n/a si8234ab-d-im1 pwm 5 v n/a si8234bb-d-im1 8 v n/a si8235ab-d-im1 via,vib dual driver 5 v n/a si8235bb-d-im1 8 v n/a 5 kv ordering options si8230bd-d-is via, vib high side/ low side 0.5 a 8 v 5.0 kvrms C40 to +125 c soic-16 wide body n/a si8231bd-d-is pwm high side/ low side si8232bd-d-is via, vib dual driver si8233bd-d-is via, vib high side/ low side 4.0 a si8234bd-d-is pwm high side/ low side si8235bd-d-is via, vib dual driver si823x data sheet ordering guide silabs.com | building a more connected world. rev. 2.1.1 | 3
ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temp range package type legacy ordering part number (opn) 2.5 kv only si8230ad-d-is via, vib high side/ low side 0.5 a 5 v 5.0 kvrms C40 to +125 c soic-16 wide body n/a si8231ad-d-is pwm n/a si8232ad-d-is via, vib dual driver n/a si8233ad-d-is via, vib high side/ low side 4.0 a 5 v n/a si8234ad-d-is pwm n/a si8235ad-d-is via, vib dual driver n/a si8230ad-d-is3 via, vib high side/ low side 0.5 a soic-14 wide body with increased creepage n/a si8230bd-d-is3 via, vib 8 v n/a si8233ad-d-is3 via, vib 4.0 a 5 v n/a si8233bd-d-is3 via, vib 8 v n/a si8235ad-d-is3 via, vib dual driver 5 v n/a si8235bd-d-is3 via, vib 8 v n/a 3 v vddi ordering options si8237ab-d-is1 via, vib dual driver 0.5 a 5 v 2.5 kvrms C40 to +125 c soic-16 narrow body n/a si8237bb-d-is1 via, vib dual driver 8 v si8238ab-d-is1 via, vib dual driver 4.0 a 5 v si8238bb-d-is1 via, vib dual driver 8 v si8237ad-d-is via, vib dual driver 0.5 a 5 v 5.0 kvrms soic-16 wide body si8237bd-d-is via, vib dual driver 8 v si8238ad-d-is via, vib dual driver 4.0 a 5 v si8238bd-d-is via, vib dual driver 8 v si8238ad-d-is3 via, vib dual driver 5 v soic-14 wide body with increased creepage si8238bd-d-is3 via, vib dual driver 8 v 1. all packages are rohs-compliant with peak reflow temperatures of 260 c according to the jedec industry standard classifica- tions and peak solder temperatures. 2. si and si are used interchangeably. 3. an "r" at the end of the part number denotes tape and reel packaging option. si823x data sheet ordering guide silabs.com | building a more connected world. rev. 2.1.1 | 4
automotive grade opns automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and low defectivity. these devices are supported with aiag-compliant production part approval process (ppap) documentation, and fea- ture international material data system (imds) and china automotive material data system (camds) listing. qualifications are compli- ant with aec-q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro- duction steps. table 1.2. ordering guide for automotive grade opns 1, 2, 4, 5 ordering part num- ber (opn) inputs configuration peak cur- rent uvlo voltage isolation rating temp range package type wide body (wb) package options si8233bb-as via, vib high side/low side 4.0 a 8 v 2.5 kvrms C40 to +125 c soic-16 wide body narrow body (nb) package options si8230bb-as1 via, vib high side/low side 0.5 a 8 v 2.5 kvrms C40 to +125 c soic-16 narrow body SI8233BB-AS1 via, vib high side/low side 4.0 a 8 v 2.5 kvrms C40 to +125 c soic-16 narrow body si8235bb-as1 via, vib high side/low side 4.0 a 8 v 2.5 kvrms C40 to +125 c soic-16 narrow body si8233ab-as1 via, vib high side/low side 4.0 a 5 v 2.5 kvrms C40 to +125 c soic-16 narrow body lga package option si8235bb-am via, vib dual driver 4.0 a 8 v 2.5 kvrms C40 to +125 c lga-14 5x5 mm 5 kv ordering options si8233bd-as via, vib high side/low side 4.0 a 8 v 5.0 C40 to +125 c soic-16 wide body si8235bd-as via, vib dual driver 4.0 a 8 v 5.0 C40 to +125 c soic-16 wide body 3 v vddi ordering options si8238bb-as1 via, vib dual driver 4.0 a 8 v 2.5 kvrms C40 to +125 c soic-16 narrow body si8238bd-as via, vib dual driver 4.0 a 8 v 5.0 kvrms C40 to +125 c soic-16 wide body note: 1. all packages are rohs-compliant with peak reflow temperatures of 260 c according to the jedec industry standard classifica- tions. 2. si and si are used interchangeably. 3. an "r" at the end of the part number denotes tape and reel packaging option. 4. automotive-grade devices (with an "Ca" suffix) are identical in construction materials, topside marking, and electrical parameters to their industrial-grade (with a "Ci" suffix) version counterparts. automotive-grade products are produced utilizing full automotive process flows and additional statistical process controls throughout the manufacturing flow. the automotive-grade part number is included on shipping labels. 5. additional ordering part numbers may be available in automotive-grade. please contact your local silicon labs sales represen- tative for further information. si823x data sheet ordering guide silabs.com | building a more connected world. rev. 2.1.1 | 5
table of contents 1. ordering guide ..............................2 2. system overview ..............................8 2.1 top level block diagrams ..........................8 2.2 functional description ........................... 10 2.3 typical operating characteristics (0.5 amp) .................... 11 2.4 typical operating characteristics (4.0 amp) .................... 14 2.5 family overview and logic operation during startup ................ 16 2.5.1 products ............................. 16 2.5.2 device behavior ........................... 17 2.6 power supply connections ......................... 18 2.7 power dissipation considerations ....................... 19 2.8 layout considerations ........................... 20 2.9 undervoltage lockout operation ....................... 21 2.9.1 device startup ........................... 21 2.9.2 undervoltage lockout ......................... 21 2.9.3 undervoltage lockout (uvlo) ...................... 21 2.9.4 control inputs ............................ 22 2.9.5 disable input ............................ 22 2.10 programmable dead time and overlap protection ................. 23 3. electrical specifications .......................... 25 3.1 test circuits .............................. 28 4. applications ............................... 34 4.1 high-side/low-side driver ......................... 34 4.2 dual driver ............................... 35 5. pin descriptions ............................. 36 6. package outlines ............................. 42 6.1 package outline: 16-pin wide body soic .................... 42 6.2 package outline: 14-pin wide body soic .................... 44 6.3 package outline: 16-pin narrow body soic ................... 46 6.4 package outline: 14 ld lga (5 x 5 mm) ..................... 47 6.5 package outline: 14 ld qfn ......................... 48 7. land patterns .............................. 49 7.1 land pattern: 16-pin wide body soic ..................... 49 7.2 land pattern: 14-pin wide body soic ..................... 50 7.3 land pattern: 16-pin narrow body soic ..................... 51 7.4 land pattern: 14 ld lga/qfn ........................ 52 silabs.com | building a more connected world. rev. 2.1.1 | 6
8. top markings .............................. 53 8.1 si823x top marking (14/16-pin wide body soic) .................. 53 8.2 si823x top marking (16-pin narrow body soic) .................. 54 8.3 si823x top marking (14 ld lga/qfn) ..................... 55 9. revision history ............................. 56 silabs.com | building a more connected world. rev. 2.1.1 | 7
2. system overview 2.1 top level block diagrams si8230/3 uvlo uvlo gndi vib vddi via vdda voa gnda vob vddi vddi i s o l a t i o n vddi vddb gndb disable i s o l a t i o n uvlo dt control & overlap protection dt figure 2.1. si8230/3 two-input high-side/low-side isolated drivers si823x data sheet system overview silabs.com building a more connected world. rev. 2.1.1 8
si8231/4 uvlo uvlo gndi vddi pwm vdda voa gnda vob vddi vddi i s o l a t i o n vddi vddb gndb disable i s o l a t i o n uvlo dt control & overlap protection dt lpwm lpwm figure 2.2. si8231/4 single-input high-side/low-side isolated drivers si8232/5/7/8 uvlo vdda voa gnda vob vddi i s o l a t i o n vddi vddb gndb uvlo via i s o l a t i o n uvlo gndi vib vddi vddi disable figure 2.3. si8232/5/7/8 dual isolated drivers si823x data sheet system overview silabs.com building a more connected world. rev. 2.1.1 9
2.2 functional description the operation of an si823x channel is analogous to that of an optocoupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si823x channel is shown in the figure below. rf oscillator modulator demodulator a b semiconductor- base d isolation barrier transmitter receiver dead time control 0.5 to 4 a peak gnd v dd driver figure 2.4. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driver. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. see the figure below for more details. input signal output signal modulation signal figure 2.5. modulation scheme si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 10
2.3 typical operating characteristics (0.5 amp) the typical performance characteristics depicted in figure 2.6 rise/fall time vs. supply voltage on page 11 through figure 2.15 output source current vs. temperature on page 12 are for information purposes only. refer to table 3.1 electrical characteris- tics 1 on page 25 for actual specification limits. 0 2 4 6 8 10 9 12 15 18 21 24 rise/fall time (ns) vdda supply (v) 25 c c l = 100 pf tfall trise figure 2.6. rise/fall time vs. supply voltage 10 15 20 25 30 9 12 15 18 21 24 propagation delay (ns) vdda supply (v) h-l l-h 25 c c l = 100 pf figure 2.7. propagation delay vs. supply voltage 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 rise/fall time (ns) load (nf) vdd=12 v , 25 c tfall trise figure 2.8. rise/fall time vs. load 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 propagation delay (ns) load (nf) vdd=12 v, 25 c h-l l- h figure 2.9. propagation delay vs. load si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 11
10 15 20 25 30 -45 -20 5 30 55 80 105 130 propagation delay (ns) temperature (c) vdd=12 v, load = 200 pf l-h h-l figure 2.10. propagation delay vs. temperature 1 2 3 4 5 -45 -20 5 30 55 80 105 130 vdda = 15 v, f = 250 khz, c l = 0 pf duty cycle = 50% 2 channels switching temperature ( c) supply current (ma) figure 2.11. supply current vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 9 14 19 24 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1 mhz 500 khz 100 khz 50 khz figure 2.12. supply current vs. supply voltage 0 1 2 3 4 5 6 7 9 14 19 24 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1 mhz 500 khz 100 khz 50 khz figure 2.13. supply current vs. supply voltage 250 300 350 400 450 500 9 14 19 24 source current (ma) supply voltage (v) vout=vdd -5 v figure 2.14. output source current vs. supply voltage 250 275 300 325 350 375 400 425 -45 -20 5 30 55 80 105 130 source current (ma) temperature (c) vdd=12 v, vout=vdd -5 v figure 2.15. output source current vs. temperature si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 12
500 625 750 875 1000 1125 9 14 19 24 sink current (ma) supply voltage (v) vout=5 v figure 2.16. output sink current vs. supply voltage 500 600 700 800 900 -45 -20 5 30 55 80 105 130 sink current (ma) temperature (c) vdd=12 v, vout=5 v figure 2.17. output sink current vs. temperature si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 13
2.4 typical operating characteristics (4.0 amp) the typical performance characteristics depicted in figure 2.18 rise/fall time vs. supply voltage on page 14 through figure 2.27 output source current vs. temperature on page 15 are for information purposes only. refer to table 3.1 electrical characteris- tics 1 on page 25 for actual specification limits. 0 2 4 6 8 10 9 12 15 18 21 24 rise/fall time (ns) vdda supply (v) 25 c c l = 100 pf tfall trise figure 2.18. rise/fall time vs. supply voltage 10 15 20 25 30 9 12 15 18 21 24 propagation delay (ns) vdda supply (v) h - l l- h 25 c c l = 100 pf figure 2.19. propagation delay vs. supply voltage 0 10 20 30 40 0 2 4 6 8 10 rise/fall time (ns) load (nf) vdd=12v , 25 c tfall trise figure 2.20. rise/fall time vs. load 10 20 30 40 50 0 2 4 6 8 10 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h figure 2.21. propagation delay vs. load si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 14
10 15 20 25 30 -45 -20 5 30 55 80 105 130 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h figure 2.22. propagation delay vs. temperature 0 2 4 6 8 10 -45 -20 5 30 55 80 105 130 supply current (ma) temperature ( c) vdda = 15v, f = 250khz,c l = 0 pf duty cycle = 50% 2 channels switching figure 2.23. supply current vs. temperature 0 2 4 6 8 10 12 14 9 12 15 18 21 24 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz figure 2.24. supply current vs. supply voltage 0 2 4 6 8 10 12 14 9 12 15 18 21 24 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz figure 2.25. supply current vs. supply voltage 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 9 12 15 18 21 24 source current (a) supply voltage (v) vout=vdd -5v figure 2.26. output source current vs. supply voltage 2 2.25 2.5 2.75 3 3.25 3.5 -45 -20 5 30 55 80 105 130 source current (a) temperature ( c) vdd=12v, vout=vdd - 5v figure 2.27. output source current vs. temperature si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 15
4 5 6 7 8 9 9 12 15 18 21 24 sink current (a) supply voltage (v) vout=5v figure 2.28. output sink current vs. supply voltage 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 -45 -20 5 30 55 80 105 130 sink current (a) temperature (c) vdd=12v, vout=5v figure 2.29. output sink current vs. temperature 2.5 family overview and logic operation during startup the si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 2.5.1 products the table below shows the configuration and functional overview for each product in this family. table 2.1. si823x family overview part number configuration overlap protection programmable dead time inputs peak output cur- rent (a) si8230 high-side/low-side via, vib 0.5 si8231 high-side/low-side pwm 0.5 si8232/7 dual driver via, vib 0.5 si8233 high-side/low-side via, vib 4.0 si8234 high-side/low-side pwm 4.0 si8235/8 dual driver via, vib 4.0 si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 16
2.5.2 device behavior the table below consists of truth tables for the si8230/3, si8231/4, and si8232/5/7/8 families. table 2.2. si823x family truth table 1 si8230/3 (high-side/low-side) truth table inputs vddi state disable output notes via vib voa vob l l powered l l l output transition occurs after internal dead time expires. l h powered l l h output transition occurs after internal dead time expires. h l powered l h l output transition occurs after internal dead time expires. h h powered l l l invalid state. output transition occurs after internal dead time expires. x 2 x 2 unpowered x l l output returns to input state within 7 s of vddi power re- storation. x x powered h l l device is disabled. si8231/4 (pwm input high-side/low-side) truth table pwm input vddi state disable output notes voa vob h powered l h l output transition occurs after internal dead time expires. l powered l l h output transition occurs after internal dead time expires. x 2 unpowered x l l output returns to input state within 7 s of vddi power re- storation. x powered h l l device is disabled. si8232/5/7/8 (dual driver) truth table inputs vddi state disable output notes via vib voa vob l l powered l l l output transition occurs immediately (no internal dead time). l h powered l l h output transition occurs immediately (no internal dead time). h l powered l h l output transition occurs immediately (no internal dead time). h h powered l h h output transition occurs immediately (no internal dead time). x 2 x 2 unpowered x l l output returns to input state within 7 s of vddi power re- storation. x x powered h l l device is disabled. notes: 1. this truth table assumes vdda and vddb are powered. if vdda and vddb are below uvlo, see 2.9 undervoltage lockout operation for more information. 2. note that an input can power the input die through an internal diode if its source has adequate current. si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 17
2.6 power supply connections isolation requirements mandate individual supplies for vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd and gnd pins of the si823x as possible. the optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 18
2.7 power dissipation considerations proper system design must assure that the si823x operates within safe thermal limits across the entire load range.the si823x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by the series gate resistor and load. equation 1 shows total si823x power dissipation. p d = ( v ddi )( i ddi ) + 2 ( i dd2 )( v dd2 ) + ( f )( q tl )( v dd2 ) r p r p + r g + ( f )( q tl )( v dd2 ) r p r p + r g + 2fcintv dd 2 2 where: p d is the total si823x device power dissipation (w) i ddi is the input-side maximum bias current (3 ma) i dd2 is the driver die maximum bias current (2.5 ma) c int is the internal parasitic capacitance (75 pf for the 0.5 a driver and 370 pf for the 4.0 a driver) vddi is the input-side vdd supply voltage (2.7 to 5.5 v) v dd2 is the driver-side supply voltage (10 to 24 v) f is the switching frequency (hz) q tl is the gate charge of the fet being driven r g is the external gate resistor r p is the r ds(on) of the driver pull-up switch: (rp = 15 ? for the 0.5 a driver; rp = 2.7 ? for the 4.0 a driver) r n is the r ds(on) of the driver pull-down switch: (rn = 5 ? for the 0.5 a driver and 1 ? for the 4.0 a driver) equation 1 power dissipation example for 0.5 a driver using equation 1 with the following givens: v ddi = 5.0 v v dd2 = 12 v f = 350 khz r g = 22 q tl = 25 nc p d = 0.015 + 0.060 + ( 350 10 3 ) ( 25 10 ? 9 ) ( 12 ) 5 5 + 22 + 2 ( 350 10 3 )( 75 10 ? 12 ) (144 ) = 145 mw from which the driver junction temperature is calculated using equation 2, where: pd is the total si823x device power dissipation (w) ja is the thermal resistance from junction to air (105 c/w in this example) t a is the ambient temperature t j = p d j a t a = ( 0.145 )( 105 ) + 20 = 35.2 o c the maximum power dissipation allowable for the si823x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in equation 2: p dmax t jmax ? t a ja where: si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 19
p dmax = maximum si823x power dissipation (w) t jmax = si823x maximum junction temperature (150 c) t a = ambient temperature (c) ja = si823x junction-to-air thermal resistance (105 c/w) f = si823x switching frequency (hz) equation 2 substituting values for p dmax t jmax , t a , and ja into equation 2 results in a maximum allowable total power dissipation of 1.19 w. maxi- mum allowable load is found by substituting this limit and the appropriate data sheet values from table 3.1 electrical characteristics 1 on page 25 into equation 1 and simplifying. the result is equation 3 (0.5 a driver) and equation 4 (4.0 a driver), both of which as- sume vddi = 5 v and vdda = vddb = 18 v. c l(max) = 1.4 10 ? 3 f ? 7.5 10 ? 11 equation 3 c l(max) = 1.4 10 ? 3 f ? 3.7 10 ? 10 equation 4 equation 3 and equation 4 are graphed in the figure below, where the points along the load line represent the package dissipation- limited value of cl for the corresponding switching frequency. 2.8 layout considerations it is most important to minimize ringing in the drive path and noise on the si823x vdd lines. care must be taken to minimize parasitic inductance in these paths by locating the si823x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split ground plane sys- tem having separate ground and vdd planes for power devices and small signal components provides the best overall noise perform- ance. si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 20
2.9 undervoltage lockout operation device behavior during start-up, normal operation and shutdown is shown in figure 2.30 device behavior during normal operation and shutdown on page 21 , where uvlo+ and uvlo- are the positive-going and negative-going thresholds respectively. note that outputs voa and vob default low when input side power supply (vddi) is not present. 2.9.1 device startup outputs voa and vob are held low during power-up until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs via and vib. 2.9.2 undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own undervoltage lockout monitors. the si823x input side enters uvlo when vddi < vddi uvC , and exits uvlo when vddi > vddi uv+ . the driver outputs, voa and vob, remain low when the input side of the si823x is in uvlo and their respective vdd supply (vdda, vddb) is within tolerance. each driver output can enter or exit uvlo independently. for example, voa unconditionally enters uvlo when vdda falls below vdda uvC and exits uvlo when vdda rises above vdda uv+ . via voa disable vddi uvlo- vdda tstart tstart tstart tsd trestart tphl tplh uvlo+ uvlo- uvlo+ tsd vdd hys vdd hys figure 2.30. device behavior during normal operation and shutdown 2.9.3 undervoltage lockout (uvlo) the uvlo circuit unconditionally drives vo low when vdd is below the lockout threshold. upon power up, the si823x is maintained in uvlo until vdd rises above vdd uv+ . during power down, the si823x enters uvlo when vdd falls below the uvlo threshold plus hysteresis (i.e., vdd < vdd uv+ C vdd hys ). si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 21
2.9.4 control inputs via, vib, and pwm inputs are high-true, ttl level-compatible logic inputs. a logic high signal on via or vib causes the corresponding output to go high. for pwm input versions (si8231/4), voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. 2.9.5 disable input when brought high, the disable input unconditionally drives voa and vob low regardless of the states of via and vib. device opera- tion terminates within tsd after disable =v ih and resumes within trestart after disable = v il . the disable input has no effect if vddi is below its uvlo level (i.e., voa, vob remain low). si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 22
2.10 programmable dead time and overlap protection all high-side/low-side drivers (si8230/1/3/4) include programmable overlap protection to prevent outputs voa and vob from being high at the same time. these devices also include programmable dead time, which adds a user-programmable delay between transitions of voa and vob. when enabled, dead time is present on all transitions, even after overlap recovery. the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per equation 5. note that the dead time pin can be tied to vddi or left floating to provide a nominal dead time at approximately 400 ps. dt 10 rdt where: dt = dead time (ns) and rdt = dead time programing resistor (k ?) equation 5 the device driving via and vib should provide a minimum dead time of tdd to avoid activating overlap protection. input/output timing waveforms for the two-input drivers are shown in figure 2.31 input / output waveforms for high-side / low-side two-input drivers on page 23 , and dead time waveforms are shown in figure 2.32 dead time waveforms for high-side / low-side two-input drivers on page 24 . figure 2.31. input / output waveforms for high-side / low-side two-input drivers si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 23
via/ pwm vib voa vob dt dt 10% 10% 90% 90% 50% vob a. typical dead time operation via/ pwm voa vob dt dt vib dt dt overlap overlap b. dead time operation during overlap figure 2.32. dead time waveforms for high-side / low-side two-input drivers si823x data sheet system overview silabs.com | building a more connected world. rev. 2.1.1 | 24
3. electrical specifications table 3.1. electrical characteristics 1 2.7 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v, ta = C40 to +125 c, typical specs at 25 c, t j = -40 to +150 c parameter symbol test condition min typ max unit dc specifications input-side power supply voltage vddi si8230/1/2/3/4/5 si8237/8 4.5 2.7 5.5 5.5 v driver supply voltage vdda, vddb voltage between vdda and gnda, and vddb and gndb (see 1. ordering guide ) 6.5 24 v input supply quiescent current iddi(q) si8230/2/3/5/7/8 2 3 ma si8231/4 3.5 5 ma output supply quiescent current idda(q), iddb(q) current per channel 3.0 ma input supply active current iddi input freq = 500 khz, no load 3.5 ma output supply active current idda iddb current per channel with input freq = 500 khz, no load 6 ma input pin leakage current ivia, ivib, ipwm C10 +10 a dc input pin leakage current (si8230/1/2/3/4/5) idisable C10 +10 a dc input pin leakage current (si8237/8) -1000 +1000 logic high input threshold vih 2.0 v logic low input threshold vil 0.8 v input hysteresis vi hyst si8230/1/2/3/4/5/7/8 400 450 mv logic high output voltage voah, vobh ioa, iob = C1 ma (vdda / vddb) 0.04 v logic low output voltage voal, vobl ioa, iob = 1 ma 0.04 v output short-circuit pulsed sink current ioa(scl), iob(scl) si8230/1/2/7, figure 3.1 iol sink current test circuit on page 28 0.5 a si8233/4/5/8, figure 3.1 iol sink current test circuit on page 28 4.0 a output short-circuit pulsed source current ioa(sch), iob(sch) si8230/1/2/7, figure 3.2 ioh source current test circuit on page 28 0.25 a si8233/4/5/8, figure 3.2 ioh source current test circuit on page 28 2.0 a si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 25
parameter symbol test condition min typ max unit output sink resistance r on(sink) si8230/1/2/7 5.0 si8233/4/5/8 1.0 output source resistance r on(source) si8230/1/2/7 15 si8233/4/5/8 2.7 vddi undervoltage threshold vddi uv+ vddi rising (si8230/1/2/3/4/5) 3.60 4.0 4.45 v vddi undervoltage threshold vddi uvC vddi falling (si8230/1/2/3/4/5) 3.30 3.70 4.15 v vddi lockout hysteresis vddi hys (si8230/1/2/3/4/5) 250 mv vddi undervoltage threshold vddi uv+ vddi rising (si8237/8) 2.15 2.3 2.5 v vddi undervoltage threshold vddi uvC vddi falling (si8237/8) 2.10 2.22 2.40 v vddi lockout hysteresis vddi hys (si8237/8) 75 mv vdda, vddb undervoltage threshold vdda uv+ , vddb uv+ vdda, vddb rising 5 v threshold 5.20 5.80 6.30 v 8 v threshold 7.50 8.60 9.40 v 10 v threshold 9.60 11.1 12.2 v 12.5 v threshold 12.4 13.8 14.8 v vdda, vddb undervoltage threshold vdda uvC , vddb uvC vdda, vddb falling 5 v threshold 4.90 5.52 6.0 v 8 v threshold 7.20 8.10 8.70 v 10 v threshold 9.40 10.1 10.9 v 12.5 v threshold 11.6 12.8 13.8 v vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 5 v 280 mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 8 v 600 mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 10 v or 12.5 v 1000 mv ac specifications minimum pulse width 10 ns propagation delay t phl , t plh cl = 200 pf 30 45 ns pulse width distortion |t plh - t phl | pwd 5.60 ns minimum overlap time 2 tdd dt = vddi, no-connect 0.4 ns si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 26
parameter symbol test condition min typ max unit programmed dead time 3 dt figure 2.32 dead time wave- forms for high-side / low-side two-input drivers on page 24 , rdt = 100 k 730 900 1170 ns figure 2.32 dead time wave- forms for high-side / low-side two-input drivers on page 24 , rdt = 6 k 55 70 75 ns output rise and fall time t r ,t f c l = 200 pf (si8230/1/2/7) 20 ns c l = 200 pf (si8233/4/5/8) 12 ns shutdown time from disable true t sd 60 ns restart time from disable false t restart 60 ns device start-up time t start time from vdd_ = vdd_uv+ to voa, vob = via, vib 40 s common mode transient immunity cmti via, vib, pwm = vddi or 0 v v cm = 1500 v (see figure 3.3 common mode transient immunity test circuit on page 29) 20 45 kv/s notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without triggering overlap protection (si8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k. si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 27
3.1 test circuits figures figure 3.1 iol sink current test circuit on page 28 , figure 3.2 ioh source current test circuit on page 28 , and figure 3.3 common mode transient immunity test circuit on page 29 depict sink current, source current, and common-mode transient im- munity test circuits, respectively. input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 15 v in out vss vdd schottky 50 ns 200 ns measure input waveform gnd vddi vddi 8 v + _ figure 3.1. iol sink current test circuit input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 15 v in out vss vdd 50 ns 200 ns measure input waveform gnd vddi schottky vddi 5.5 v + _ figure 3.2. ioh source current test circuit si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 28
oscilloscope 5v isol ated supply vdda voa gnda 12 v supply high voltage surge generator vcm surge output 100k high voltage differential probe vddb vob gndb dt gndi vddi input dis able input signal switch input output isolated gr ound si823x figure 3.3. common mode transient immunity test circuit table 3.2. regulatory information 1 csa the si823x is certified under csa component acceptance notice 5a. for more details, see master contract number 232873. 60950-1, 62368-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. 60601-1: up to 250 v rms working voltage and 2 mopp (means of patient protection). vde the si823x is certified according to vde 0884-10 and en 60950-1. for more details, see certificates 40018443, 40030763. 0884-10: up to 891 vpeak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. ul the si823x is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si823x is certified under gb4943.1-2011. for more details, see certificates cqc13001096106, cqc13001096108, and cqc 17001178087. rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 29
note: 1. regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. regulatory certifi- cations apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see 1. ordering guide . table 3.3. insulation and safety-related specifications parameter symbol test condition value unit wbsoic-14/16 5 kv rms wbsoic-14/16 nbsoic-16 2.5 kv rms 14 ld lga /qfn 2.5 kv rms nominal external air gap (clearance) 1 clr 8.0 8.0/4.01 3.5 mm nominal external track- ing (creepage) 1 cpg 8.0 8.0/4.01 3.5 mm minimum internal gap (internal clearance) dti 0.014 0.014 0.014 mm tracking resistance cti or pti iec60112 600 600 600 v erosion depth ed 0.019/0.122 0.019/0.122 0.021 mm resistance (input-output) 2 r io 10 12 10 12 10 12 capacitance (input-output) 2 c io f = 1 ?z 1.4 1.4 1.4 pf input capacitance 3 c i 4.0 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in 6.1 package outline: 16-pin wide body soic, 6.2 package outline: 14-pin wide body soic , 6.3 package outline: 16-pin narrow body soic , 6.4 package outline: 14 ld lga (5 x 5 mm), 6.5 package outline: 14 ld qfn . vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic and 8.5 mm minimum for the wb soic package. ul does not impose a clearance and creepage mini- mum for component level certifications. csa certifies the clearance and creepage of the wb soic package with designation "is3" as 8 mm minimum. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic and 7.6 mm mini- mum for the wb soic package with package designation "is" as listed in the data sheet. 2. to determine resistance and capacitance, the si823x is converted into a 2-terminal device. pins 1C8 (1C7, 14 ld lga/qfn) are shorted together to form the first terminal and pins 9C16 (8C14, 14 ld lga/qfn) are shorted together to form the second termi- nal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 30
table 3.4. iec 60664-1 ratings parameter test condition specification wb soic-14/16 nb soic-16 14 ld lga/qfn basic isolation group material group i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iii i-iii rated mains voltages < 400 v rms i-iii i-ii i-ii rated mains voltages < 600 v rms i-iii i-ii i-ii table 3.5. vde 0884-10 insulation characteristics 1 parameter symbol test condition characteristic unit wb soic-14/16 nb soic-16 14 ld lga/qfn maximum working insu- lation voltage v iorm 891 560 v peak input to output test volt- age v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1671 1050 v peak transient overvoltage v iotm t = 60 s 6000 4000 v peak surge voltage v iosm tested per iec 60065 with surge voltage of 1.2 s/50 s si823xxb/c/d tested with 4000 v 3077 3077 3077 vpeak pollution degree (din vde 0110, table 1) 2 2 insulation resistance at t s , v io = 500 v r s >10 9 >10 9 *note: 1. maintenance of the safety data is ensured by protective circuits. the si823x provides a climate classification of 40/125/21. si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 31
table 3.6. vde 0884-10 safety limiting values 1 parameter symbol test condition wb soic-14/16 nb soic-16 14 ld lga/qfn unit case temperature t s 150 150 150 c safety input current s ja = 100 c/w (wb so- ic-14/16), 105 c/w (nb soic-16, 14 ld lga/qfn) v ddi = 5.5 v, v dda = v ddb = 24 v, t j = 150 c, t a = 25 c 50 50 50 ma device power dissipa- tion 2 p d 1.2 1.2 1.2 w notes: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in figures figure 3.4 wb soic, nb soic, 14 ld lga/qfn thermal derating curve, dependence of safety limiting values with case temperature per vde 0884-10 on page 32 . 2. the si82xx is tested with v ddi = 5.5 v, v dda = v ddb = 24 v, t j = 150 oc, c l = 100 pf, input 2 mhz 50% duty cycle square wave. table 3.7. thermal characteristics parameter symbol wb soic-14/16 nb soic-16 14 ld lga/qfn unit ic junction-to-air thermal resistance ja 100 105 105 c/w 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vddi = 5.5 v vdda, vddb = 24 v 10 30 50 figure 3.4. wb soic, nb soic, 14 ld lga/qfn thermal derating curve, dependence of safety limiting values with case temperature per vde 0884-10 si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 32
table 3.8. absolute maximum ratings 1 parameter symbol min max unit storage temperature 2 t stg C65 +150 c ambient temperature under bias t a C40 +125 c junction temperature t j +150 c input-side supply voltage vddi C0.6 6.0 v driver-side supply voltage vdda, vddb C0.6 30 v voltage on any pin with respect to ground v io C0.5 vdd + 0.5 v peak output current (t pw = 10 s, duty cycle = 0.2%) (0.5 amp versions) i opk 0.5 a peak output current (t pw = 10 s, duty cycle = 0.2%) (4.0 amp versions) i opk 4.0 a lead solder temperature (10 s) 260 c maximum isolation (input to out- put) (1 s) wb soic 6500 v rms maximum isolation (output to out- put) (1 s) wb soic 2500 v rms maximum isolation (input to out- put) (1 s) nb soic 4500 v rms maximum isolation (output to out- put) (1 s) nb soic 2500 v rms maximum isolation (input to out- put) (1 s) 14 ld lga/qfn 3850 v rms maximum isolation (output to out- put) (1 s) 14 ld lga/qfn 650 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 2. vde certifies storage temperature from C40 to 150 c. si823x data sheet electrical specifications silabs.com | building a more connected world. rev. 2.1.1 | 33
4. applications the following examples illustrate typical circuit configurations using the si823x. 4.1 high-side/low-side driver the figure a in the drawing below shows the si8230/3 controlled using the via and vib input signals, and figure b shows the si8231/4 controlled by a single pwm signal. si8230/3 cb 1500 v max gndi vddi via vdda voa gnda vob vddi disable vdd2 dt rdt controller vib c1 1 f out1 out2 i/o q1 q2 d1 vddb c3 1 f si8231/4 cb pwm vdda voa gnda vob disable dt rdt controller pwmout i/o q1 q2 d1 a b vdd2 c3 1 f 1500 v max c2 0.1 f gndi vddi vddi c1 1 f c2 0.1 f vddb gndb c4 0.1 f c5 10 f vddb gndb c4 0.1 f c5 10 f figure 4.1. si823x in half-bridge application for both cases, d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 1500 v. the boot-strap start up time will depend on the cb cap chosen. see application note, an486: high- side bootstrap design using si823x isodrivers in power delivery systems. vob is connected as a conventional low-side driver, and, in most cases, vdd2 is the same as vddb. note that the input side of the si823x requires vdd in the range of 4.5 to 5.5 v (2.7 to 5.5 v for si8237/8), while the vdda and vddb output side supplies must be between 6.5 and 24 v with respect to their respective grounds. it is recommended that bypass capacitors of 0.1 and 1 f value be used on the si823x input side and that they be located as close to the chip as possible. moreover, it is recommended that 0.1 and 10 f bypass capacitors, located as close to the chip as possi- ble, be used on the si823x output side to reduce high-frequency noise and maximize performance. si823x data sheet applications silabs.com | building a more connected world. rev. 2.1.1 | 34
4.2 dual driver the figure below shows the si823x configured as a dual driver. note that the drain voltages of q1 and q2 can be referenced to a com- mon ground or to different grounds with as much as 1500 v dc between them. si8232/5/7/8 via vdda voa gnda vob vddb gndb disable controller vib ph1 ph2 i/o q1 q2 vdda vddb gndi vddi vddi c1 1 f c2 0.1 f c5 0.1 f c6 10 f c3 0.1 f c4 10 f figure 4.2. si8232/5/7/8 in a dual driver application because each output driver resides on its own die, the relative voltage polarities of voa and vob can reverse without damaging the driver. that is, the voltage at voa can be higher or lower than that of vob by vdd without damaging the driver. therefore, a dual driver in a low-side high side/low side drive application can use either voa or vob as the high side driver. similarly, a dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes. si823x data sheet applications silabs.com | building a more connected world. rev. 2.1.1 | 35
5. pin descriptions via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8230 si8233 soic-16 (wide) via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8230 si8233 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 table 5.1. si8230/3 two-input hs/ls isolated driver (soic-16). wb soic-14 with is3 package designation, has pins 12 & 13 missing pin name description 1 via non-inverting logic input terminal for driver a. 2 vib non-inverting logic input terminal for driver b. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input unconditionally drives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid er- roneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 400 ps dead time when connected to vddi or left open (see 2.10 programmable dead time and overlap protection ). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. si823x data sheet pin descriptions silabs.com | building a more connected world. rev. 2.1.1 | 36
pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 soic-16 (wide) pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 table 5.2. si8231/4 pwm input hs/ls isolated driver (soic-16). wb soic-14 with is3 package designation, has pins 12 & 13 missing pin name description 1 pwm pwm input. 2 nc no connection. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input unconditionally drives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid er- roneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 400 ps dead time when connected to vddi or left open (see 2.10 programmable dead time and overlap protection ). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. si823x data sheet pin descriptions silabs.com | building a more connected world. rev. 2.1.1 | 37
via nc vddi gndi disable nc vib vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235 si8237 si8238 soic-16 (wide) via vib vddi gndi disable nc nc vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235 si8237 si8238 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 table 5.3. si8232/5/7/8 dual isolated driver (soic-16). wb soic-14 with is3 package designation, has pins 12 & 13 missing pin name description 1 via non-inverting logic input terminal for driver a. 2 vib non-inverting logic input terminal for driver b. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v, (2.7 to 5.5 v for si8237/8). 4 gndi input-side ground terminal. 5 disable device disable. when high, this input unconditionally drives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid er- roneous operation due to capacitive noise coupling. 6 nc no connection. 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v, (2.7 to 5.5 v for si8237/8). 9 gndb ground terminal for driver b. 10 vob driver b output. 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output. 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. si823x data sheet pin descriptions silabs.com | building a more connected world. rev. 2.1.1 | 38
lga-14 and qfn-14 (5 x 5 mm) gndi via vib vddi disable dt vddi vdda voa gnda nc vddb vob gndb si8233 1 2 3 4 5 6 7 14 13 12 11 10 9 8 table 5.4. si8233 two-input hs/ls isolated driver (14 ld lga and qfn) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic input terminal for driver a. vib 3 non-inverting logic input terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally drives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid er- roneous operation due to capacitive noise coupling. dt 6 dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 400 ps dead time when connected to vddi or left open (see 2.10 programmable dead time and overlap protection ). vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. si823x data sheet pin descriptions silabs.com | building a more connected world. rev. 2.1.1 | 39
lga-14 and qfn-14 (5 x 5 mm) gndi pwm nc vddi disable dt vddi vdda voa gnda nc vddb vob gndb si8234 1 2 3 4 5 6 7 14 13 12 11 10 9 8 table 5.5. si8234 pwm input hs/ls isolated driver (14 ld lga and qfn) pin name description gndi 1 input-side ground terminal. pwm 2 pwm input. nc 3 no connection. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally drives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid er- roneous operation due to capacitive noise coupling. dt 6 dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 400 ps dead time when connected to vddi or left open (see 2.10 programmable dead time and overlap protection ). vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. si823x data sheet pin descriptions silabs.com | building a more connected world. rev. 2.1.1 | 40
lga-14 and qfn-14 (5 x 5 mm) gndi via vib vddi disable nc vddi vdda voa gnda nc vddb vob gndb si8235 1 2 3 4 5 6 7 14 13 12 11 10 9 8 table 5.6. si8235 dual isolated driver (14 ld lga and qfn) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic input terminal for driver a. vib 3 non-inverting logic input terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally drives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid er- roneous operation due to capacitive noise coupling. nc 6 no connection. vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. si823x data sheet pin descriptions silabs.com | building a more connected world. rev. 2.1.1 | 41
6. package outlines 6.1 package outline: 16-pin wide body soic figure 6.1 16-pin wide body soic on page 42 illustrates the package details for the si823x in a 16-pin wide body soic. table 6.1 package diagram dimensions on page 42 lists the values for the dimensions shown in the illustration. figure 6.1. 16-pin wide body soic table 6.1. package diagram dimensions dimension min max a 2.65 a1 0.10 0.30 a2 2.05 b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 0 8 si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 42
dimension min max 0.10 bbb 0.33 ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per jedec j-std-020 specification for small body, lead-free components. si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 43
6.2 package outline: 14-pin wide body soic figure 6.2 si823x 14-pin wb soic outline on page 44 illustrates the package details for the si823x in a 14-pin wide body soic. table 6.2 package diagram dimensions on page 44 lists the values for the dimensions shown in the illustration. figure 6.2. si823x 14-pin wb soic outline table 6.2. package diagram dimensions dimension min max a 2.65 a1 0.10 0.30 a2 2.05 b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 0 ? 8 ? aaa 0.10 bbb 0.33 ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 44
dimension min max notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per jedec j-std-020 specification for small body, lead-free components. si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 45
6.3 package outline: 16-pin narrow body soic figure 6.3 16-pin small outline integrated circuit (soic) package on page 46 illustrates the package details for the si823x in a 16- pin narrow-body soic. table 6.3 package diagram dimensions on page 46 lists the values for the dimensions shown in the illustra- tion. figure 6.3. 16-pin small outline integrated circuit (soic) package table 6.3. package diagram dimensions dimension min max dimension min max a 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 h 0.25 0.50 b 0.31 0.51 0 8 c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 46
6.4 package outline: 14 ld lga (5 x 5 mm) figure 6.4 si823x lga outline on page 47 illustrates the package details for the si823x in an lga outline. table 6.4 package dia- gram dimensions on page 47 lists the values for the dimensions shown in the illustration. figure 6.4. si823x lga outline table 6.4. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 5.00 bsc d1 4.15 bsc e 0.65 bsc e 5.00 bsc e1 3.90 bsc l 0.70 0.75 0.80 l1 0.05 0.10 0.15 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.15 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 47
6.5 package outline: 14 ld qfn figure 6.5 si823x 14-pin ld qfn outline on page 48 illustrates the package details for the si823x in an qfn outline. table 6.5 package diagram dimensions on page 48 lists the values for the dimensions shown in the illustration. figure 6.5. si823x 14-pin ld qfn outline table 6.5. package diagram dimensions dimension min nom max a 0.74 0.85 0.90 a1 0 0.025 0.05 b 0.25 0.30 0.35 d 5.00 bsc e 0.65 bsc e 5.00 bsc e1 3.60 bsc l 0.50 0.60 0.70 l1 3 0.10 bsc ccc 0.08 ddd 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. l1 shall not be less than 0.01 mm. si823x data sheet package outlines silabs.com | building a more connected world. rev. 2.1.1 | 48
7. land patterns 7.1 land pattern: 16-pin wide body soic figure 7.1 16-pin soic land pattern on page 49 illustrates the recommended land pattern details for the si823x in a 16-pin wide- body soic. table 7.1 16-pin wide body soic land pattern dimensions on page 49 lists the values for the dimensions shown in the illustration. figure 7.1. 16-pin soic land pattern table 7.1. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protru- sion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si823x data sheet land patterns silabs.com | building a more connected world. rev. 2.1.1 | 49
7.2 land pattern: 14-pin wide body soic figure 7.2 14-pin wb soic land pattern on page 50 illustrates the recommended land pattern details for the si823x in a 14-pin wide body soic. table 7.2 14-pin wb soic land pattern dimensions on page 50 lists the values for the dimensions shown in the illustration. figure 7.2. 14-pin wb soic land pattern table 7.2. 14-pin wb soic land pattern dimensions dimension feature (mm) c1 pad column spacing 4.20 e pad row pitch 1.50 x1 pad width 4.25 y1 pad length 0.65 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protru- sion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si823x data sheet land patterns silabs.com | building a more connected world. rev. 2.1.1 | 50
7.3 land pattern: 16-pin narrow body soic figure 7.3 16-pin narrow body soic pcb land pattern on page 51 illustrates the recommended land pattern details for the si823x in a 16-pin narrow-body soic. table 7.3 16-pin narrow body soic land pattern dimensions on page 51 lists the values for the dimen- sions shown in the illustration. figure 7.3. 16-pin narrow body soic pcb land pattern table 7.3. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si823x data sheet land patterns silabs.com | building a more connected world. rev. 2.1.1 | 51
7.4 land pattern: 14 ld lga/qfn figure 7.4 14-pin lga/qfn land pattern on page 52 illustrates the recommended land pattern details for the si823x in a 14-pin lga/ qfn. table 7.4 14-pin lga/qfn land pattern dimensions on page 52 lists the values for the dimensions shown in the illustration. figure 7.4. 14-pin lga/qfn land pattern table 7.4. 14-pin lga/qfn land pattern dimensions dimension (mm) c1 4.20 e 0.65 x1 0.80 y1 0.40 notes: general 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabri- cation allowance of 0.05 mm. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si823x data sheet land patterns silabs.com | building a more connected world. rev. 2.1.1 | 52
8. top markings 8.1 si823x top marking (14/16-pin wide body soic) table 8.1. top marking explanation (14/16-pin wide body soic) line 1 marking: base part number ordering options see ordering guide for more information. si823 = isodriver product series y = peak output current 0, 1, 2, 7 = 0.5 a 3, 4, 5, 8 = 4.0 a u = uvlo level a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating b = 2.5 kv; c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. line 3 marking: circle = 1.5 mm diameter (center justified) e4 pb-free symbol country of origin iso code abbreviation tw = taiwan (as shown), th = thailand si823x data sheet top markings silabs.com | building a more connected world. rev. 2.1.1 | 53
8.2 si823x top marking (16-pin narrow body soic) line 1 marking: base part number ordering options see ordering guide for more information. si823 = isodriver product series y = peak output current 0, 1, 2, 7 = 0.5 a 3, 4, 5, 8 = 4.0 a u = uvlo level a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating a = 1.0 kv; b = 2.5 kv; c = 3.75 kv line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. si823x data sheet top markings silabs.com | building a more connected world. rev. 2.1.1 | 54
8.3 si823x top marking (14 ld lga/qfn) line 1 marking: base part number ordering options see ordering guide for more information. si823 = isodriver product series y = peak output current 0, 1, 2 = 0.5 a 3, 4, 5 = 4.0 a line 2 marking: ordering options u = uvlo level a = 5 v; b = 8 v; c = 10 v; d = 12.5 v v = isolation rating a = 1.0 kv; b = 2.5 kv; c = 3.75 kv i = C40 to +125 c ambient temperature range m = lga package type m1 = qfn package type line 3 marking: tttttt manufacturing code from assembly line 4 marking: circle = 1.5 mm diameter pin 1 identifier yyww manufacturing date code si823x data sheet top markings silabs.com | building a more connected world. rev. 2.1.1 | 55
9. revision history revision 2.1.1 january 2018 ? added new table to ordering guide for automotive-grade opn options. revision 2.1 october 2017 ? added is3 and im1 packaging options ? added iec 62368-1 references throughout ? changed max propagation delay spec from 60 ns to 45 ns based on new test limits ? removed references to iec 61010 ? removed references to iec 60747, replaced with references to vde 0884-10 revision 2.0 august 7, 2017 revision 1.9 july 7, 2017 ? updated 1. ordering guide to designate tape and reel packaging option. revision 1.8 may 17, 2016 ? converted document from framemaker to dita. revision 1.7 ? updated 3.1 test circuits ? added cqc certificate numbers. ? updated table 3.3 insulation and safety-related specifications on page 30 ? updated erosion depth. ? updated table 3.5 vde 0884-10 insulation characteristics 1 on page 31 ? updated v pr for wbsoic-16. ? updated table 3.8 absolute maximum ratings 1 on page 33 ? removed io and added peak output current specifications. ? updated equation 1. ? updated figure 4.1 si823x in half-bridge application on page 34 . ? updated figure 4.2 si8232/5/7/8 in a dual driver application on page 35 . ? updated ordering guide table 1.1 si823x ordering guide 1, 2, 3 on page 2 revision 1.6 ? updated table 1.1 si823x ordering guide 1, 2, 3 on page 2 , ordering part numbers. ? added revision d ordering part numbers. ? removed all ordering part numbers of previous revisions. revision 1.5 ? updated table 3.1 electrical characteristics 1 on page 25 , input and output supply current. ? added references to aec-q100 qualified throughout. ? changed all 60747-5-2 references to 60747-5-5. ? added references to cqc throughout. ? updated pin descriptions throughout. ? corrected dead time default to 400 ps from 1 ns. ? updated table 1.1 si823x ordering guide 1, 2, 3 on page 2 , ordering part numbers. ? removed moisture sensitivity level table notes. si823x data sheet revision history silabs.com | building a more connected world. rev. 2.1.1 | 56
revision 1.4 ? updated 1. ordering guide . ? updated "3 v vddi ordering options". revision 1.3 ? added si8237/8 throughout. ? updated table 3.1 electrical characteristics 1 on page 25 . ? updated figure 3.1 iol sink current test circuit on page 28 . ? updated figure 3.2 ioh source current test circuit on page 28 . ? added figure 3.3 common mode transient immunity test circuit on page 29 . ? updated si823x family truth table to include notes 1 and 2. ? updated 2.10 programmable dead time and overlap protection . ? removed references to figures 26a and 26b. ? updated table 1.1 si823x ordering guide 1, 2, 3 on page 2. ? added si8235-ba-c-is1 ordering part number. ? added table note. revision 1.2 ? updated 1. ordering guide . ? updated moisture sensitivity level (msl) for all package types. ? updated table 3.8 absolute maximum ratings 1 on page 33 . ? added junction temperature spec. ? updated 3.1 test circuits with new notes. ? updated figures figure 2.16 output sink current vs. supply voltage on page 13 , figure 2.14 output source current vs. supply voltage on page 12 , figure 2.17 output sink current vs. temperature on page 13 , and figure 2.15 output source current vs. tem- perature on page 12 to reflect correct y-axis scaling. ? updated figure 4.2 si8232/5/7/8 in a dual driver application on page 35 . ? updated . ? updated 6.1 package outline: 16-pin wide body soic . ? updated table 6.1 package diagram dimensions on page 42 . ? change references to 1.5 kv rms rated devices to 1.0 kv rms throughout. ? updated 2.7 power dissipation considerations . revision 1.1 ? updated . ? updated cmti specification. ? updated table 3.1 electrical characteristics 1 on page 25 . ? updated cmti specification. ? updated table 3.5 vde 0884-10 insulation characteristics 1 on page 31 . ? updated 4.2 dual driver . ? updated 1. ordering guide . ? replaced pin descriptions on page 1 with chip graphics. revision 1.0 ? updated tables 3.1 test circuits , table 3.3 insulation and safety-related specifications on page 30 , table 3.4 iec 60664-1 rat- ings on page 31 , and table 3.5 vde 0884-10 insulation characteristics 1 on page 31 . ? updated 1. ordering guide . ? added 5 v uvlo ordering options ? added device marking sections. si823x data sheet revision history silabs.com | building a more connected world. rev. 2.1.1 | 57
revision 0.3 ? moved sections 2, 3, and 4 to after section 5. ? updated tables table 5.4 si8233 two-input hs/ls isolated driver (14 ld lga and qfn) on page 39 , table 5.5 si8234 pwm input hs/ls isolated driver (14 ld lga and qfn) on page 40 . ? removed si8230, si8231, and si8232 from pinout and from title. ? updated and added ordering guide footnotes. ? updated uvlo specifications in table 3.1 electrical characteristics 1 on page 25 . ? added pwd and output supply active current specifications in table 3.1 electrical characteristics 1 on page 25 . ? updated and added typical operating condition graphs in 2.3 typical operating characteristics (0.5 amp) and 2.4 typical operating characteristics (4.0 amp) . revision 0.2 ? updated all specs to reflect latest silicon revision. ? updated table 3.1 electrical characteristics 1 on page 25 to include new uvlo options. ? updated table 3.8 absolute maximum ratings 1 on page 33 to reflect new maximum package isolation ratings ? added figures 34, 35, and 36. ? updated ordering guide to reflect new package offerings. ? added "undervoltage lockout (uvlo)" section to describe uvlo operation. revision 0.11 ? initial release. si823x data sheet revision history silabs.com | building a more connected world. rev. 2.1.1 | 58
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